module i2s_receiver_array(
	input  wire        clk_50m,
    input  wire        rst_n,
    input  wire [15:0] i2s_sdata,      // 16个数据线
    output wire        i2s_bclk,       // 共享位时钟
    output wire        i2s_lrclk,      // 共享帧时钟
    
    output wire [23:0] mic_data [15:0], // 16通道24位数据
    output wire        data_vld [15:0], // 16通道数据有效
    output wire        frame_sync,      // 帧同步信号
    output wire [3:0]  debug_state     // 调试状态
 );

// 子模块实例化
generate
    for (genvar i = 0; i < 16; i = i + 1) begin : i2s_receivers
        i2s_receiver_single u_rx (
            .clk_50m(clk_50m),
            .rst_n(rst_n),
            .i2s_sdata(i2s_sdata[i]),
            .i2s_bclk(i2s_bclk),
            .i2s_lrclk(i2s_lrclk),
            .rx_data(mic_data[i]),
            .rx_vld(data_vld[i])
        );
    end
endgenerate

// 帧同步检测
frame_sync_detector u_sync_detector (
    .clk(i2s_bclk),
    .rst_n(rst_n),
    .data_vld(data_vld),
    .frame_sync(frame_sync)
);

endmodule
